1. Field
This disclosure relates generally to error detection for an execution unit of a processor and, more particularly, to residue-based error detection for a processor execution unit that supports vector operations.
2. Related Art
Today, it is common for processors to be designed to detect errors. For example, one known processor design has implemented two identical processor pipelines. In this processor design, processor errors are detected by comparing results of the two identical processor pipelines. While duplicating processor pipelines improves error detection, duplicating processor pipelines is relatively expensive in terms of integrated circuit (chip) area and chip power consumption. A less expensive technique (e.g., in terms of chip area and power consumption) for detecting errors in an execution unit of a processor has employed residue checking.
Residue-based error detection (or residue checking) has been widely employed in various applications. For example, U.S. Pat. No. 3,816,728 (hereinafter “the '728 patent”) discloses a modulo 9 residue checking circuit for detecting errors in decimal addition operations. As another example, U.S. Pat. No. 4,926,374 (hereinafter “the '374 patent”) discloses a residue checking apparatus that is configured to detect errors in addition, subtraction, multiplication, division, and square root operations. As yet another example, U.S. Pat. No. 7,555,692 (hereinafter “the '692 patent”) discloses logic for computing residues for full-sized data and reduce-sized data.